ON Semiconductor 4598 free download

File name 4598.pdf

MC14598B 8-Bit Bus-Compatible Latches The MC14598B is an 8­bit latch addressed with an external binary address. The 8 latch­outputs are high drive, three­state and bus line compatible. The drive capability allows direct applications with MPU systems such as the Motorola 6800 family. The latches of the MC14598B are accessed via the Address pins, A0, A1, and A2. All 8 outputs from the latches are available in parallel when Enable is in the low state. Data is entered into a selected latch from the Data pin when the Strobe is high. Master reset is available on both parts. http://onsemi.com · · · · · · · · · Serial Data Input Three­State Bus Compatible Parallel Outputs Three­State Control Pin (Enable) TTL Compatible Input Open Drain Full Flag (Multiple Latch Wire­O Ring) Master Reset Level Shifting Inputs on All Except Enable Diode Protection -- All Inputs Supply Voltage Range -- 3.0 Vdc to 18 Vdc Capable of Driving TTL Over Rated Temperature Range With Fanout as Follows: 1 TTL Load 4 LSTTL Loads 18 PDIP­18 P SUFFIX CASE 707 1 A WL, L YY, Y WW, W MARKING DIAGRAMS MC14598BCP AWLYYWW = Assembly Location = Wafer Lot = Year = Work Week MAXIMUM RATINGS (Voltages Referenced to VSS) (Note 1.) Symbol VDD Vin Vin Vout Iin, Iout PD TA Tstg TL Parameter DC Supply Voltage Range Input Voltage Range, Enable (DC or Transient) Input Voltage Range, All Other Inputs (DC or Transient) Output Voltage Range, (DC or Transient) Input or Output Current (DC or Transient) per Pin Power Dissipation, per Package (Note 2.) Ambient Temperature Range Storage Temperature Range Lead Temperature (8­Second Soldering) Value ­0.5 to +18.0 ­0.5 to VDD + 0.5 ­0.5 to VDD + 12 ­0.5 to VDD + 0.5 ±10 500 ­55 to +125 ­65 to +150 260 Unit V V V V mA mW °C °C °C ORDERING INFORMATION Device MC14598BCP Package PDIP­18 Shipping 20/Rail 1. Maximum Ratings are those values beyond which damage to the device may occur. 2. Temperature Derating: Plastic "P and D/DW" Packages: ­ 7.0 mW/_C From 65_C To 125_C This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high­impedance circuit. For proper operation, Vin and Vout should be constrained to the range VSS v (Vin or Vout) v VDD. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VDD). Unused outputs must be left open. © Semiconductor Components Industries, LLC, 2000 1 August, 2000 ­ Rev. 4 Publication Order Number: MC14598B/D MC14598B PIN ASSIGNMENT D0 RESET DATA ENABLE NC STROBE A0 A1 VSS 1 2 3 4 5 6 7 8 9 18 17 16 15 14 13 12 11 10 VDD D1 D2 D3 D4 D5 D6 D7 A2 BLOCK DIAGRAMS MC14598B RESET DATA STROBE A0 A1 A2 7 8 ADDRESS 10 DECODER VDD = 18 VSS = 9 2 3 6 8 LATCHES ENABLE 4 1 17 16 15 14 13 12 11 D0 D1 D2 D3 D4 D5 D6 D7 OUTPUT TRUTH TABLE Enable 1 0 Outputs High Impedance Dn THREE STATE OUTPUT BUFFERS Dn = State of nth lat